979 search results - page 52 / 196 » Optimal instruction scheduling using integer programming |
ISCAPDCS
2001
13 years 11 months ago
2001
This paper presents the evaluation of a non-blocking, decoupled memory/execution, multithreaded architecture known as the Scheduled Dataflow (SDF). The major recent trend in digit...
MICRO
2008
IEEE
14 years 4 months ago
2008
IEEE
— Processor architectures with large instruction windows have been proposed to expose more instruction-level parallelism (ILP) and increase performance. Some of the proposed arch...
ARC
2009
Springer
14 years 4 months ago
2009
Springer
This paper argues the case for the use of analytical models in FPGA architecture layout exploration. We show that the problem when simplified, is amenable to formal optimization t...
DCC
2007
IEEE
14 years 9 months ago
2007
IEEE
Instruction and data address traces are widely used by computer designers for quantitative evaluations of new architectures and workload characterization, as well as by software de...
MICRO
2000
IEEE
14 years 2 months ago
2000
IEEE
Value prediction breaks data dependencies in a program thereby creating instruction level parallelism that can increase program performance. Hardware based value prediction techni...