Sciweavers

979 search results - page 9 / 196
» Optimal instruction scheduling using integer programming
Sort
View
IEEEPACT
2000
IEEE
14 years 2 months ago
Exploring the Limits of Sub-Word Level Parallelism
Multimedia instruction set extensions have become a prominent feature in desktop microprocessor platforms, promising superior performance on a wide range of floating-point and int...
Kevin Scott, Jack W. Davidson
DATE
2002
IEEE
137views Hardware» more  DATE 2002»
14 years 2 months ago
Practical Instruction Set Design and Compiler Retargetability Using Static Resource Models
The design of application (-domain) specific instructionset processors (ASIPs), optimized for code size, has traditionally been accompanied by the necessity to program assembly, ...
Qin Zhao, Bart Mesman, Twan Basten
ISCA
2002
IEEE
102views Hardware» more  ISCA 2002»
14 years 2 months ago
Implementing Optimizations at Decode Time
The number of pipeline stages separating dynamic instruction scheduling from instruction execution has increased considerably in recent out-of-order microprocessor implementations...
Ilhyun Kim, Mikko H. Lipasti
ISLPED
1998
ACM
79views Hardware» more  ISLPED 1998»
14 years 2 months ago
Voltage scheduling problem for dynamically variable voltage processors
This paper presents a model of dynamically variable voltage processor and basic theorems for power-delay optimization. A static voltage scheduling problem is also proposed and for...
Tohru Ishihara, Hiroto Yasuura
DAC
2006
ACM
14 years 10 months ago
Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming
In this paper, we propose an exact algorithm for the problem of area optimization under a delay constraint in the synthesis of multiplierless FIR filters. To the best of our knowl...
Eduardo A. C. da Costa, José Monteiro, Leve...