Sciweavers

378 search results - page 20 / 76
» Optimal integrated code generation for VLIW architectures
Sort
View
DAC
2006
ACM
14 years 2 months ago
Buffer memory optimization for video codec application modeled in Simulink
Reduction of the on-chip memory size is a key issue in video codec system design. Because video codec applications involve complex algorithms that are both data-intensive and cont...
Sang-Il Han, Xavier Guerin, Soo-Ik Chae, Ahmed Ami...
CODES
2005
IEEE
14 years 2 months ago
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
Girish Venkataramani, Tiberiu Chelcea, Seth Copen ...
CASES
2007
ACM
14 years 12 days ago
SCCP/x: a compilation profile to support testing and verification of optimized code
Embedded systems are often used in safety-critical environments. Thus, thorough testing of them is mandatory. A quite active research area is the automatic test-case generation fo...
Raimund Kirner
TCSV
2002
119views more  TCSV 2002»
13 years 8 months ago
VLSI architecture design of MPEG-4 shape coding
This paper presents an efficient VLSI architecture design of MPEG-4 shape coding, which is the key technology for supporting the content-based functionality of the MPEG-4 Video sta...
Hao-Chieh Chang, Yung-Chi Chang, Yi-Chu Wang, Wei-...
LCPC
2001
Springer
14 years 26 days ago
The Structure of a Compiler for Explicit and Implicit Parallelism
Abstract. We describe the structure of a compilation system that generates code for processor architectures supporting both explicit and implicit parallel threads. Such architectur...
Seon Wook Kim, Rudolf Eigenmann