378 search results - page 64 / 76 » Optimal integrated code generation for VLIW architectures |
DAC
2010
ACM
13 years 11 months ago
2010
ACM
Complex embedded systems have always been heterogeneous multicore systems. Because of the tight constraints on power, performance and cost, this situation is not likely to change a...
CGO
2010
IEEE
14 years 2 months ago
2010
IEEE
The linear scan algorithm for register allocation provides a good register assignment with a low compilation overhead and is thus frequently used for just-in-time compilers. Altho...
LCTRTS
2007
Springer
14 years 1 months ago
2007
Springer
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
ASAP
2007
IEEE
14 years 1 months ago
2007
IEEE
With increasing reliability concerns for current and next generation VLSI technologies, fault-tolerance is fast becoming an integral part of system-on-chip and multicore architect...
DSD
2006
IEEE
13 years 11 months ago
2006
IEEE
Abstract-- Networks-on-Chip will serve as the central integration platform in future complex SoC designs, composed of a large number of heterogeneous processing resources. Most res...