51 search results - page 4 / 11 » Optimization Techniques for ADL-Driven RTL Processor Synthes... |
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
: Common sub-expression elimination (CSE) serves as a useful optimization technique in the synthesis of arithmetic datapaths described at RTL. However, CSE has a limited potential ...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intend...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle ...
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
— Architecture Description Languages (ADLs) are widely used to perform design space exploration for Application Specific Instruction Set Processors (ASIPs). While the design spa...
ASAP
1997
IEEE
13 years 11 months ago
1997
IEEE
This paper reviews a set of techniques for compiling dataflow-based, graphical programs for embedded signal processing applications into efficient implementations on programmable ...