60 search results - page 5 / 12 » Optimization of Area and Delay at Gate-Level in Multiple Con... |
DATE
2010
IEEE
13 years 6 months ago
2010
IEEE
Abstract—On-chip interconnection network is a crucial design component in high-performance System-on-Chips (SoCs). Many of previous works have focused on the automation of its to...
CORR
2007
Springer
13 years 7 months ago
2007
Springer
In this paper, we consider an automatic-repeat-request (ARQ) retransmission protocol signaling over a block-fading multiple-input, multiple-output (MIMO) channel. Unlike previous ...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Carry Save Adder (CSA) trees are commonly used for high speed implementation of multi-operand additions. We present a method to reduce the number of the adders in CSA trees by ext...
DAC
2000
ACM
14 years 8 months ago
2000
ACM
Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. Semiconductor Industry Association (SIA) roadmap predicts that, beyond the ...
ICCD
2001
IEEE
14 years 4 months ago
2001
IEEE
Dynamic power is the main source of power consumption in CMOS circuits. It depends on the square of the supply voltage. It may significantly be reduced by scaling down the supply ...