70 search results - page 11 / 14 » Optimization of combinational and sequential logic circuits ... |
FPGA
2006
ACM
14 years 6 days ago
2006
ACM
This report describes a preliminary evaluation of possible performance of an FPGA-like architecture for future hybrid "CMOL" circuits which combine a semiconductor-trans...
DATE
2003
IEEE
14 years 1 months ago
2003
IEEE
In modern SoCs, embedded memories occupy the largest part of the chip area and include an even larger amount of active devices. As memories are designed very tightly to the limits...
SIGCSE
2009
ACM
14 years 9 months ago
2009
ACM
ion and Extensibility in Digital Logic Simulation Software Richard M. Salter and John L. Donaldson Computer Science Department Oberlin College Oberlin, OH 44074 rms@cs.oberlin.edu,...
GLVLSI
2003
IEEE
14 years 1 months ago
2003
IEEE
A new split accumulator architecture to be used in direct digital frequency synthesizers (DDFS) systems is presented. This new design eliminates the need of adders on the section ...
DAC
2005
ACM
14 years 9 months ago
2005
ACM
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...