66 search results - page 13 / 14 » Optimization of critical paths in circuits with level-sensit... |
GLVLSI
2003
IEEE
14 years 25 days ago
2003
IEEE
In this paper, we describe a low power and high speed multiplier suitable for standard cell-based ASIC design methodologies. For the purpose, an optimized booth encoder, compact 2...
MICRO
2008
IEEE
14 years 1 months ago
2008
IEEE
Processors progressively age during their service life due to normal workload activity. Such aging results in gradually slower circuits. Anticipating this fact, designers add timi...
HPCA
2008
IEEE
14 years 8 months ago
2008
IEEE
The continued scaling of device dimensions and the operating voltage reduces the critical charge and thus natural noise tolerance level of transistors. As a result, circuits can p...
ICCAD
2007
IEEE
14 years 4 months ago
2007
IEEE
— Starting at the 65nm node, stress engineering to improve performance of transistors has been a major industry focus. An intrinsic stress source – shallow trench isolation –...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global. In particular, flexible...