66 search results - page 4 / 14 » Optimization of critical paths in circuits with level-sensit... |
GLVLSI
1998
IEEE
13 years 12 months ago
1998
IEEE
In this paper we address the problem of optimizing mixed CMOS BiCMOS circuits. The problem is formulated as a constrained combinatorial optimization problem and solved using an ta...
ICCAD
2000
IEEE
13 years 11 months ago
2000
IEEE
ct Static timing analysis has traditionally used the PERT method for identifying the critical path of a digital circuit. Due to the influence of the slope of a signal at a particul...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
— Criticality and yield gradients are two crucial diagnostic metrics obtained from Statistical Static Timing Analysis (SSTA). They provide valuable information to guide timing op...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
A fundamental problem in timing-driven physical synthesis is the reduction of critical paths in a design. In this work, we propose a powerful new technique that moves (and can als...
ASPDAC
2000
ACM
13 years 12 months ago
2000
ACM
We propose a circuit performance oriented device optimization methodology using pre-silicon parameters and critical paths which represent the performance of the chip. Based on our...