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GECCO
2004
Springer
14 years 1 months ago
Designing Multiplicative General Parameter Filters Using Adaptive Genetic Algorithms
Multiplicative general parameter (MGP) approach to finite impulse response (FIR) filtering introduces a novel way to realize cost effective adaptive filters in compact very large s...
Jarno Martikainen, Seppo J. Ovaska
CODES
2005
IEEE
14 years 1 months ago
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
Girish Venkataramani, Tiberiu Chelcea, Seth Copen ...
ISPD
1997
ACM
110views Hardware» more  ISPD 1997»
13 years 11 months ago
Performance driven global routing for standard cell design
Advances in fabrication technology have resulted in a continual shrinkage of device dimensions. This has resulted in smaller device delays, greater resistance along interconnect w...
Jason Cong, Patrick H. Madden
GLVLSI
2007
IEEE
151views VLSI» more  GLVLSI 2007»
13 years 11 months ago
Hand-in-hand verification of high-level synthesis
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...
Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Ma...
FPGA
2006
ACM
155views FPGA» more  FPGA 2006»
13 years 11 months ago
Improvements to technology mapping for LUT-based FPGAs
The paper presents several improvements to state-of-theart in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD `04]. Improve...
Alan Mishchenko, Satrajit Chatterjee, Robert K. Br...