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DAC
1999
ACM
13 years 12 months ago
Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design
As the CMOS technology enters the deep submicron design era, the lateral inter-wire coupling capacitance becomes the dominant part of load capacitance and makes RC delay on the bu...
Joon-Seo Yim, Chong-Min Kyung
IPPS
1998
IEEE
13 years 12 months ago
The Effect of the Router Arbitration Policy on the Scalability of ServerNet
In this paper we extend a previously introduced method for optimizing the arbitration policy employed by ServerNet routers and we evaluate the method's effect on scalability....
Vladimir Shurbanov, Dimiter R. Avresky, Robert W. ...
ICCAD
1997
IEEE
144views Hardware» more  ICCAD 1997»
13 years 12 months ago
Exploiting off-chip memory access modes in high-level synthesis
Memory-intensive behaviors often contain large arrays that are synthesized into off-chip memories. With the increasing gap between on-chip and off-chip memory access delays, it is...
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nico...
ECCV
2010
Springer
13 years 11 months ago
Max-Margin Dictionary Learning for Multiclass Image Categorization
Abstract. Visual dictionary learning and base (binary) classifier training are two basic problems for the recently most popular image categorization framework, which is based on t...
CPAIOR
2006
Springer
13 years 11 months ago
The Timetable Constrained Distance Minimization Problem
We define the timetable constrained distance minimization problem (TCDMP) which is a sports scheduling problem applicable for tournaments where the total travel distance must be mi...
Rasmus V. Rasmussen, Michael A. Trick