244 search results - page 28 / 49 » Optimizing Loop Performance for Clustered VLIW Architectures |
NPC
2010
Springer
13 years 6 months ago
2010
Springer
Achieving high performance on today’s architectures requires careful orchestration of many optimization parameters. In particular, the presence of shared-caches on multicore arch...
PLDI
1995
ACM
13 years 11 months ago
1995
ACM
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
With energy consumption becoming one of the first-class optimization parameters in computer system design, compilation techniques that consider performance and energy simultaneous...
MOBICOM
2010
ACM
13 years 8 months ago
2010
ACM
Femtocell technology has been drawing considerable attention as a cost-effective means of improving cellular coverage and capacity. However, under co-channel deployment, femtocell...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
— Memory-intensive applications present unique challenges to an ASIC designer in terms of the choice of memory organization, memory size requirements, bandwidth and access latenc...