244 search results - page 6 / 49 » Optimizing Loop Performance for Clustered VLIW Architectures |
MICRO
2002
IEEE
14 years 20 days ago
2002
IEEE
Clustering is a common technique to overcome the wire delay problem incurred by the evolution of technology. Fully-distributed architectures, where the register file, the functio...
ASAP
2006
IEEE
13 years 11 months ago
2006
IEEE
State-of-the-art communication standards make extensive use of Turbo codes. The complex and power consuming designs that currently implement the turbo decoder expose the need for ...
EH
2004
IEEE
13 years 11 months ago
2004
IEEE
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
MICRO
2000
IEEE
13 years 7 months ago
2000
IEEE
High-performance microprocessors are currently designed to exploit the inherent instruction level parallelism (ILP) available in most applications. The techniques used in their de...
CF
2004
ACM
14 years 1 months ago
2004
ACM
Centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption and are thus not suitable for consumer electronic devices. The conse...