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ICRA
2005
IEEE
168views Robotics» more  ICRA 2005»
14 years 1 months ago
Control of Scalable Wet SMA Actuator Arrays
- This paper presents a new control method to drive an array of wet Shape Memory Alloy actuators utilizing a Matrix Manifold and Valve system (MMV). The MMV architecture allows a v...
L. Flemming, Stephen A. Mascaro
INFOCOM
2000
IEEE
14 years 3 days ago
Dynamic Routing of Bandwidth Guaranteed Tunnels with Restoration
— This paper presents new algorithms for dynamic routing of restorable bandwidth guaranteed paths. Dynamic routing implies routing of requests that arrive one-by-one with no a pr...
Murali S. Kodialam, T. V. Lakshman
PC
2010
196views Management» more  PC 2010»
13 years 6 months ago
Solving path problems on the GPU
We consider the computation of shortest paths on Graphic Processing Units (GPUs). The blocked recursive elimination strategy we use is applicable to a class of algorithms (such as...
Aydin Buluç, John R. Gilbert, Ceren Budak
PDPTA
2000
13 years 9 months ago
Evaluation of Neural and Genetic Algorithms for Synthesizing Parallel Storage Schemes
Exploiting compile time knowledge to improve memory bandwidth can produce noticeable improvements at run-time [13, 1]. Allocating the data structure [13] to separate memories when...
Mayez A. Al-Mouhamed, Husam Abu-Haimed
GLVLSI
2009
IEEE
189views VLSI» more  GLVLSI 2009»
14 years 2 months ago
High-performance, cost-effective heterogeneous 3D FPGA architectures
In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a...
Roto Le, Sherief Reda, R. Iris Bahar