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ASPDAC
2007
ACM
98views Hardware» more  ASPDAC 2007»
13 years 12 months ago
Fast Analytic Placement using Minimum Cost Flow
Many current integrated circuits designs, such as those released for the ISPD2005[14] placement contest, are extremely large and can contain a great deal of white space. These new...
Ameya R. Agnihotri, Patrick H. Madden
FAST
2011
12 years 11 months ago
Cost Effective Storage using Extent Based Dynamic Tiering
Multi-tier systems that combine SSDs with SAS/FC and/or SATA disks mitigate the capital cost burden of SSDs, while benefiting from their superior I/O performance per unit cost an...
Jorge Guerra, Himabindu Pucha, Joseph S. Glider, W...
CF
2007
ACM
13 years 12 months ago
An analysis of the effects of miss clustering on the cost of a cache miss
In this paper we describe a new technique, called pipeline spectroscopy, and use it to measure the cost of each cache miss. The cost of a miss is displayed (graphed) as a histogra...
Thomas R. Puzak, Allan Hartstein, Philip G. Emma, ...
COMPSAC
2010
IEEE
13 years 5 months ago
Minimising the Preparation Cost of Runtime Testing Based on Testability Metrics
Abstract--Test cost minimisation approaches have traditionally been devoted to minimising "execution costs", while maximising coverage or reliability. However, in a runti...
Alberto González-Sanchez, Éric Piel,...
ICCAD
2008
IEEE
170views Hardware» more  ICCAD 2008»
14 years 4 months ago
A polynomial time approximation scheme for timing constrained minimum cost layer assignment
Abstract— As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasing...
Shiyan Hu, Zhuo Li, Charles J. Alpert