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ISQED
2002
IEEE
126views Hardware» more  ISQED 2002»
14 years 1 months ago
Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are ...
Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-...
ASPDAC
2004
ACM
85views Hardware» more  ASPDAC 2004»
14 years 2 months ago
Integrating buffer planning with floorplanning for simultaneous multi-objective optimization
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance and signal integrity. Buffer insertion is one...
Yi-Hui Cheng, Yao-Wen Chang
ASPDAC
2001
ACM
104views Hardware» more  ASPDAC 2001»
14 years 19 days ago
Optimal spacing and capacitance padding for general clock structures
Clock-tuning has been classified as important but tough tasks due to the non-convex nature caused by the skew requirements. As a result, all existing mathematical programming appr...
Yu-Min Lee, Hing Yin Lai, Charlie Chung-Ping Chen
SEMWEB
2010
Springer
13 years 6 months ago
Optimizing Enterprise-Scale OWL 2 RL Reasoning in a Relational Database System
OWL 2 RL was standardized as a less expressive but scalable subset of OWL 2 that allows a forward-chaining implementation. However, building an enterprise-scale forward-chaining ba...
Vladimir Kolovski, Zhe Wu, George Eadon
SIGMETRICS
2010
ACM
187views Hardware» more  SIGMETRICS 2010»
14 years 1 months ago
Can multipath mitigate power law delays?: effects of parallelism on tail performance
—Parallelism has often been used to improve the reliability and efficiency of a variety of different engineering systems. In this paper, we quantify the efficiency of paralleli...
Jian Tan, Wei Wei, Bo Jiang, Ness Shroff, Donald F...