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» Optimizing pipelines for power and performance
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ICCD
2005
IEEE
129views Hardware» more  ICCD 2005»
14 years 5 months ago
Temperature-Aware Voltage Islands Architecting in System-on-Chip Design
As technology scales, power consumption and thermal effects have become challenges for system-on-chip designers. The rising on-chip temperatures can have negative impacts on SoC p...
Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vi...
GLVLSI
2009
IEEE
112views VLSI» more  GLVLSI 2009»
14 years 2 months ago
Simultaneous shield and repeater insertion
Resource based optimization for high performance integrated circuits is presented. The methodology is applied to simultaneous shield and repeater insertion, resulting in minimum c...
Renatas Jakushokas, Eby G. Friedman
ISPAN
2009
IEEE
14 years 2 months ago
High Speed Articulated Object Tracking Using GPUs: A Particle Filter Approach
—This paper presents a novel application of the GPU processing power to a very computationally demanding articulated human body tracking problem in a view-based approach. This wo...
Raúl Cabido, David Concha, Juan José...
ISLPED
2009
ACM
97views Hardware» more  ISLPED 2009»
14 years 2 months ago
A high-performance low-power nanophotonic on-chip network
On-chip communication, including short, often-multicast, latency-critical coherence and synchronization messages, and long, unicast, throughput-sensitive data transfer, limits the...
Zheng Li, Jie Wu, Li Shang, Alan R. Mickelson, Man...
DATE
2006
IEEE
145views Hardware» more  DATE 2006»
14 years 2 months ago
Building a better Boolean matcher and symmetry detector
Boolean matching is a powerful technique that has been used in technology mapping to overcome the limitations of structural pattern matching. The current basis for performing Bool...
Donald Chai, Andreas Kuehlmann