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» Optimizing pipelines for power and performance
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BROADNETS
2004
IEEE
13 years 11 months ago
The Effects of the Sub-Carrier Grouping on Multi-Carrier Channel Aware Scheduling
Channel-aware scheduling and link adaptation (LA) methods are widely considered to be crucial for realizing high data rates in wireless networks. Multi-carrier systems that spread...
Fanchun Jin, Gokhan Sahin, Amrinder Arora, Hyeong-...
WWW
2007
ACM
14 years 8 months ago
Long distance wireless mesh network planning: problem formulation and solution
Several research efforts as well as deployments have chosen IEEE 802.11 as a low-cost, long-distance access technology to bridge the digital divide. In this paper, we consider the...
Sayandeep Sen, Bhaskaran Raman
HPCA
2009
IEEE
14 years 8 months ago
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...
DSD
2009
IEEE
84views Hardware» more  DSD 2009»
14 years 2 months ago
Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures
— 3D stacked architectures provide significant benefits in performance, footprint and yield. However, vertical stacking increases the thermal resistances, and exacerbates tempe...
Ayse Kivilcim Coskun, Andrew B. Kahng, Tajana Simu...
ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 29 days ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...