2048 search results - page 3 / 410 » Optimizing pipelines for power and performance |
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
—This paper presents a method to optimize the power consumption of a pipelined ADC with kT/C noise constraint. The total power dependence on capacitor scaling and stage resolutio...
ICCD
2002
IEEE
14 years 4 months ago
2002
IEEE
A method of managing the power consumption of an embedded, single-issue processor by controlling its pipeline depth is proposed. The execution time will be increased but, if the m...
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
In many workloads, 25% to 50% of instructions have slack allowing them to be delayed without impacting performance. To exploit this slack, processors may implement more power-efï¬...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
- For modern processor designs in nanometer technologies, both block and interconnect pipelining are needed to achieve multi-gigahertz clock frequency, but previous approaches cons...