1990 search results - page 14 / 398 » Optimizing the Instruction Cache Performance of the Operatin... |
DATE
2000
IEEE
13 years 12 months ago
2000
IEEE
With the ongoing advancements in VLSI technology, the performance of an embedded system is determined to a large extend by the communication of data and instructions. This results...
PLDI
1995
ACM
13 years 11 months ago
1995
ACM
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
CCGRID
2008
IEEE
14 years 2 months ago
2008
IEEE
The advances in multicore technology and modern interconnects is rapidly accelerating the number of cores deployed in today’s commodity clusters. A majority of parallel applicat...
MICRO
2000
IEEE
13 years 7 months ago
2000
IEEE
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
IEEEPACT
2007
IEEE
14 years 1 months ago
2007
IEEE
We present a detailed characterization of instruction cache performance for IBM’s J2EE-enabled web server, WebSphere Application Server (WAS). When running two J2EE benchmarks o...