1990 search results - page 16 / 398 » Optimizing the Instruction Cache Performance of the Operatin... |
ASPDAC
2004
ACM
14 years 29 days ago
2004
ACM
— The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting their special architecture features. Beside the ...
ICPP
2002
IEEE
14 years 15 days ago
2002
IEEE
Conventional instruction fetch mechanisms fetch contiguous blocks of instructions in each cycle. They are difficult to scale since taken branches make it hard to increase the siz...
DAC
1998
ACM
14 years 8 months ago
1998
ACM
Memory is one of the most restricted resources in many modern embedded systems. Code compression can provide substantial savings in terms of size. In a compressed code CPU, a cach...
CASES
2010
ACM
13 years 5 months ago
2010
ACM
We present a fine-grain dynamic instruction placement algorithm for small L0 scratch-pad memories (spms), whose unit of transfer can be an individual instruction. Our algorithm ca...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Some instructions have more impact on processor performance than others. Identification of these critical instructions can be used to modify and improve instruction processing. Pr...