1990 search results - page 7 / 398 » Optimizing the Instruction Cache Performance of the Operatin... |
ECRTS
2006
IEEE
14 years 1 months ago
2006
IEEE
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
MICRO
2002
IEEE
14 years 12 days ago
2002
IEEE
Instruction cache aware compilation seeks to lay out a program in memory in such a way that cache conflicts between procedures are minimized. It does this through profile-driven...
ASPLOS
1992
ACM
13 years 11 months ago
1992
ACM
Software-controlled data prefetching is a promising technique for improving the performance of the memory subsystem to match today's high-performance processors. While prefet...
LCTRTS
2005
Springer
14 years 1 months ago
2005
Springer
Effective use of the memory hierarchy is critical for achieving high performance on embedded systems. We focus on the class of streaming applications, which is increasingly preval...
IEEEINTERACT
2002
IEEE
14 years 13 days ago
2002
IEEE
A dynamic optimizer is a software-based system that performs code modifications at runtime, and several such systems have been proposed over the past several years. These systems ...