337 search results - page 3 / 68 » Optimizing yield in global routing |
ISPD
1999
ACM
13 years 12 months ago
1999
ACM
—This paper studies a natural formulation of the timing-driven maze routing problem. A multigraph model appropriate for global routing applications is adopted; the model naturall...
ICCD
2007
IEEE
14 years 1 months ago
2007
IEEE
A methodology for constructing circuit-level mismatch models and performing yield optimization is presented for CMOS analog circuits. The methodology combines statistical techniqu...
SPAA
2003
ACM
14 years 23 days ago
2003
ACM
The increasing application space of interconnection networks now encompasses several applications, such as packet routing and I/O interconnect, where the throughput of a routing a...
CDES
2006
13 years 9 months ago
2006
The ability to improve the yield of integrated circuits through layout modification has been recognized and several techniques for yield enhanced routing and compaction have been ...
ICCAD
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper presents an efficient statistical design methodology that allows simultaneous sizing for performance and optimization for yield and robustness of analog circuits. The s...