51 search results - page 5 / 11 » Overscaling-friendly timing speculation architectures |
MICRO
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper describes FAST, a novel simulation methodology that can produce simulators that (i) are orders of magnitude faster than comparable simulators, (ii) are cycleaccurate, (...
ANSS
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper proposes a parallel cycle-accurate microarchitectural simulator which efficiently executes its workload by splitting the simulation process along time-axis into many in...
HPCA
2005
IEEE
14 years 8 months ago
2005
IEEE
This paper introduces a novel technique which leverages value prediction and multithreading on a simultaneous multithreading processor to achieve higher performance in a single th...
ISCA
1996
IEEE
13 years 11 months ago
1996
IEEE
Many studies have investigated performance improvement through exploiting instruction-level parallelism (ILP) with a particular architecture. Unfortunately, these studies indicate...
ET
2007
13 years 7 months ago
2007
In this paper, we focus on reliability, one of the most fundamental and important challenges, in the nanoelectronics environment. For a processor architecture based on the unreliab...