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» Overview on Low Power SoC Design Technology
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CODES
2004
IEEE
13 years 11 months ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan
GLVLSI
2008
IEEE
190views VLSI» more  GLVLSI 2008»
14 years 2 months ago
A low leakage 9t sram cell for ultra-low power operation
This paper presents the design and evaluation of a new SRAM cell made of nine transistors (9T). The proposed 9T cell utilizes a scheme with separate read and write wordlines; it i...
Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi
ISM
2006
IEEE
120views Multimedia» more  ISM 2006»
14 years 1 months ago
An Overview of the Use of Remote Embedded Sensors for Audio Acquisition and Processing
In recent decades, the cost of acoustic technologies has declined dramatically. Advances in networks, storage devices, and power management have made it practical to consider the ...
Lewis Girod, Marie A. Roch
CORR
2010
Springer
196views Education» more  CORR 2010»
13 years 7 months ago
Low Power Reversible Parallel Binary Adder/Subtractor
In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computin...
H. G. Rangaraju, U. Venugopal, K. N. Muralidhara, ...
ASPDAC
2004
ACM
109views Hardware» more  ASPDAC 2004»
14 years 1 months ago
Resource-constrained low-power bus encoding with crosstalk delay elimination
— In deep-submicron (DSM) technology, minimizing power consumption of a bus is one of the most important design objectives in embedded system-on-chip (SoC) design. In this paper,...
Meeyoung Cha, Chun-Gi Lyuh, Taewhan Kim