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NOCS
2008
IEEE
14 years 2 months ago
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks
In this paper, we introduce the use of slow-silent virtual channels to reduce the switching power of on-chip networks while keeping the leakage power small. Adding virtual channel...
Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang,...
ASAP
2009
IEEE
119views Hardware» more  ASAP 2009»
13 years 11 months ago
A Low Power High Performance Radix-4 Approximate Squaring Circuit
An implementation of a radix-4 approximate squaring circuit is described employing a new operand dual recoding technique. Approximate squaring circuits have numerous applications ...
Satyendra R. Datla, Mitchell A. Thornton, David W....
CORR
2010
Springer
197views Education» more  CORR 2010»
13 years 7 months ago
Modelling of Human Glottis in VLSI for Low Power Architectures
The Glottal Source is an important component of voice as it can be considered as the excitation signal to the voice apparatus. Nowadays, new techniques of speech processing such a...
Nikhil Raj, R. K. Sharma
DATE
2007
IEEE
156views Hardware» more  DATE 2007»
14 years 1 months ago
Process variation tolerant low power DCT architecture
: 2-D Discrete Cosine Transform (DCT) is widely used as the core of digital image and video compression. In this paper, we present a novel DCT architecture that allows aggressive v...
Nilanjan Banerjee, Georgios Karakonstantis, Kaushi...
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
14 years 26 days ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...