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» Overview on Low Power SoC Design Technology
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TVLSI
2002
366views more  TVLSI 2002»
13 years 7 months ago
Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits
Gate diffusion input (GDI)--a new technique of low-power digital combinatorial circuit design--is described. This technique allows reducing power consumption, propagation delay, an...
Arkadiy Morgenshtein, Alexander Fish, Israel A. Wa...
ISCAS
2006
IEEE
163views Hardware» more  ISCAS 2006»
14 years 1 months ago
ASIC hardware implementation of the IDEA NXT encryption algorithm
— Symmetric-key block ciphers are often used to provide data confidentiality with low complexity, especially in the case of dedicated hardware implementations. IDEA NXT is a nov...
Marco Macchetti, Wenyu Chen
ISSS
2002
IEEE
151views Hardware» more  ISSS 2002»
14 years 12 days ago
Tuning of Loop Cache Architectures to Programs in Embedded System Design
Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-b...
Frank Vahid, Susan Cotterell
IPPS
2006
IEEE
14 years 1 months ago
Multi-clock pipelined design of an IEEE 802.11a physical layer transmitter
Among different wireless LAN technologies 802.11a has recently become popular due to its high throughput, large system capacity, and relatively long range. In this paper, we prop...
Maryam Mizani, Daler N. Rakhmatov
ISCAS
2005
IEEE
165views Hardware» more  ISCAS 2005»
14 years 1 months ago
An area-efficient and protected network interface for processing-in-memory systems
Abstract- This paper describes the implementation of an areaefficient and protected user memory-mapped network interface, the pbuf (Parcel Buffer), for the Data IntensiVe Architect...
Sumit D. Mediratta, Craig S. Steele, Jeff Sondeen,...