138 search results - page 24 / 28 » PADded Cache: A New Fault-Tolerance Technique for Cache Memo... |
ASPLOS
2010
ACM
13 years 11 months ago
2010
ACM
Cores in a chip-multiprocessor (CMP) system share multiple hardware resources in the memory subsystem. If resource sharing is unfair, some applications can be delayed significantl...
ISCA
1993
IEEE
13 years 11 months ago
1993
IEEE
In this paper we introduce a classification of misses in shared-memory multiprocessors based on inter processor communication. We identify the set of essential misses, i.e., the s...
LCPC
2009
Springer
14 years 6 days ago
2009
Springer
Abstract. Current hardware trends place increasing pressure on programmers and tools to optimize scientific code. Numerous tools and techniques exist, but no single tool is a pana...
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
The load-store unit is a performance critical component of a dynamically-scheduled processor. It is also a complex and non-scalable component. Several recently proposed techniques...
ISCA
2000
IEEE
14 years 1 days ago
2000
IEEE
Value locality, a recently discovered program attribute that describes the likelihood of the recurrence of previously-seen program values, has been studied enthusiastically in the...