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IPPS
2010
IEEE
13 years 5 months ago
Restructuring parallel loops to curb false sharing on multicore architectures
The memory hierarchy of most multicore systems contains one or more levels of cache that is shared among multiple cores. The shared-cache architecture presents many opportunities f...
Santosh Sarangkar, Apan Qasem
HPCA
2004
IEEE
14 years 8 months ago
Using Prime Numbers for Cache Indexing to Eliminate Conflict Misses
Using alternative cache indexing/hashing functions is a popular technique to reduce conflict misses by achieving a more uniform cache access distribution across the sets in the ca...
Mazen Kharbutli, Keith Irwin, Yan Solihin, Jaejin ...
MICRO
2009
IEEE
159views Hardware» more  MICRO 2009»
14 years 2 months ago
Adaptive line placement with the set balancing cache
Efficient memory hierarchy design is critical due to the increasing gap between the speed of the processors and the memory. One of the sources of inefficiency in current caches is...
Dyer Rolán, Basilio B. Fraguela, Ramon Doal...
SIGMOD
2004
ACM
204views Database» more  SIGMOD 2004»
14 years 7 months ago
Buffering Database Operations for Enhanced Instruction Cache Performance
As more and more query processing work can be done in main memory, memory access is becoming a significant cost component of database operations. Recent database research has show...
Jingren Zhou, Kenneth A. Ross
ICPP
2003
IEEE
14 years 28 days ago
Enabling Partial Cache Line Prefetching Through Data Compression
Hardware prefetching is a simple and effective technique for hiding cache miss latency and thus improving the overall performance. However, it comes with addition of prefetch buff...
Youtao Zhang, Rajiv Gupta