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ISLPED
1998
ACM
84views Hardware» more  ISLPED 1998»
14 years 19 days ago
Low power architecture of the soft-output Viterbi algorithm
CT This paper investigates the low power implementation issues of the soft-output Viterbi algorithm (SOVA), a building block for turbo codes. By briefly explaining the theory of t...
David Garrett, Mircea R. Stan
IPPS
1998
IEEE
14 years 19 days ago
Synthesis of a Systolic Array Genetic Algorithm
The paper presents the design of a hardware genetic algorithm which uses a pipeline of systolic arrays. Demostrated is the design methodology, where a simple genetic algorithm exp...
Graham M. Megson, I. M. Bland
CORR
2010
Springer
72views Education» more  CORR 2010»
13 years 8 months ago
Porting Decision Tree Algorithms to Multicore using FastFlow
The whole computer hardware industry embraced multicores. For these machines, the extreme optimisation of sequential algorithms is no longer sufficient to squeeze the real machine ...
Marco Aldinucci, Salvatore Ruggieri, Massimo Torqu...
HPCA
1998
IEEE
14 years 20 days ago
Hardware for Speculative Run-Time Parallelization in Distributed Shared-Memory Multiprocessors
Run-time parallelization is often the only way to execute the code in parallel when data dependence information is incomplete at compile time. This situation is common in many imp...
Ye Zhang, Lawrence Rauchwerger, Josep Torrellas
JSAC
1998
110views more  JSAC 1998»
13 years 8 months ago
Turbo Decoding as an Instance of Pearl's "Belief Propagation" Algorithm
—In this paper, we will describe the close connection between the now celebrated iterative turbo decoding algorithm of Berrou et al. and an algorithm that has been well known in ...
Robert J. McEliece, David J. C. MacKay, Jung-Fu Ch...