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» Parallel Memory Architecture for Arbitrary Stride Accesses
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ICPP
1995
IEEE
13 years 11 months ago
Hiding Miss Latencies with Multithreading on the Data Diffusion Machine
— Large parallel computers require techniques to tolerate the potentially large latencies of accessing remote data. Multithreadingis onesuch technique. We extend previous studies...
Henk L. Muller, Paul W. A. Stallard, David H. D. W...
HPCA
2005
IEEE
14 years 8 months ago
A Performance Comparison of DRAM Memory System Optimizations for SMT Processors
Memory system optimizations have been well studied on single-threaded systems; however, the wide use of simultaneous multithreading (SMT) techniques raises questions over their ef...
Zhichun Zhu, Zhao Zhang
HPCA
2001
IEEE
14 years 8 months ago
Reducing DRAM Latencies with an Integrated Memory Hierarchy Design
In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory syst...
Wei-Fen Lin, Steven K. Reinhardt, Doug Burger
HPCA
2009
IEEE
14 years 8 months ago
Feedback mechanisms for improving probabilistic memory prefetching
This paper presents three techniques for improving the effectiveness of the recently proposed Adaptive Stream Detection (ASD) prefetching mechanism. The ASD prefetcher is a standa...
Ibrahim Hur, Calvin Lin
MICRO
2003
IEEE
148views Hardware» more  MICRO 2003»
14 years 25 days ago
Fast Secure Processor for Inhibiting Software Piracy and Tampering
Due to the widespread software piracy and virus attacks, significant efforts have been made to improve security for computer systems. For stand-alone computers, a key observation...
Jun Yang 0002, Youtao Zhang, Lan Gao