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» Parallel Processing Architectures for Reconfigurable Systems
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VLSID
2004
IEEE
107views VLSI» more  VLSID 2004»
14 years 9 months ago
Performance Analysis of Inter Cluster Communication Methods in VLIW Architecture
With increasing demands for high performance by embedded systems, especially by digital signal processing applications, embedded processors must increase available instruction lev...
Sourabh Saluja, Anshul Kumar
SASP
2009
IEEE
291views Hardware» more  SASP 2009»
14 years 3 months ago
FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs
— As growing power dissipation and thermal effects disrupted the rising clock frequency trend and threatened to annul Moore’s law, the computing industry has switched its route...
Alexandros Papakonstantinou, Karthik Gururaj, John...
IPPS
2007
IEEE
14 years 3 months ago
Optimizing the Fast Fourier Transform on a Multi-core Architecture
The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system softwar...
Long Chen, Ziang Hu, Junmin Lin, Guang R. Gao
VISUALIZATION
1999
IEEE
14 years 1 months ago
A Multi-Threaded Streaming Pipeline Architecture for Large Structured Data Sets
Computer simulation and digital measuring systems are now generating data of unprecedented size. The size of data is becoming so large that conventional visualization tools are in...
C. Charles Law, Ken Martin, William J. Schroeder, ...
CLOUD
2010
ACM
14 years 2 months ago
Stateful bulk processing for incremental analytics
This work addresses the need for stateful dataflow programs that can rapidly sift through huge, evolving data sets. These data-intensive applications perform complex multi-step c...
Dionysios Logothetis, Christopher Olston, Benjamin...