52 search results - page 5 / 11 » Parallel VLSI Architectures for Cryptographic Systems |
ICS
1999
Tsinghua U.
14 years 26 days ago
1999
Tsinghua U.
Supercomputer performance is highly dependent on its interconnection subsystem design. In this paper we study how di erent architectural approaches for router design impact into s...
FCCM
2011
IEEE
13 years 10 days ago
2011
IEEE
— This paper describes an architecture and FPGA synthesis toolchain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide ...
FPL
2009
Springer
14 years 1 months ago
2009
Springer
Networks-on-Chips (NoCs) are an emerging communication topology paradigm in single chip VLSI design, enhancing parallelism and system scalability. Processing units (PUs) connect t...
VLSID
2001
IEEE
14 years 9 months ago
2001
IEEE
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
VLSID
2004
IEEE
14 years 9 months ago
2004
IEEE
With increasing demands for high performance by embedded systems, especially by digital signal processing applications, embedded processors must increase available instruction lev...