462 search results - page 8 / 93 » Parallel algorithm for hardware implementation of inverse ha... |
FPL
2003
Springer
13 years 12 months ago
2003
Springer
In this paper we present a single-chip FPGA full encryptor/decryptor core design of the AES algorithm. Our design performs all of them, encryption, decryption and key scheduling pr...
DELTA
2010
IEEE
13 years 11 months ago
2010
IEEE
High level hardware description languages aim to make hardware design more like programming software. These languages are often used to accelerate legacy software algorithms by ...
ASAP
2006
IEEE
14 years 23 days ago
2006
IEEE
Current microprocessor instruction set architectures are word oriented, with some subword support. Many important applications, however, can realize substantial performance benefi...
IJCNN
2000
IEEE
13 years 11 months ago
2000
IEEE
We have fabricated a PCA (Principal Component Analysis) learning network in a FPGA (Field Programmable Gate Array) by using an asynchronous PDM (Pulse Density Modulation) digital ...
ISVLSI
2005
IEEE
14 years 9 days ago
2005
IEEE
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...