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IPPS
2003
IEEE
14 years 19 days ago
Modeling Parallel Applications Performance on Heterogeneous Systems
The current technologies have made it possible to execute parallel applications across heterogeneous platforms. However, the performance models available do not provide adequate m...
Jameela Al-Jaroodi, Nader Mohamed, Hong Jiang, Dav...
ICCAD
2009
IEEE
132views Hardware» more  ICCAD 2009»
13 years 5 months ago
DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior
Traditional circuit design focuses on optimizing the static critical paths no matter how infrequently these paths are exercised dynamically. Circuit optimization is then tuned to ...
Lu Wan, Deming Chen
IPPS
2006
IEEE
14 years 1 months ago
Multiprocessor on chip: beating the simulation wall through multiobjective design space exploration with direct execution
Design space exploration of multiprocessors on chip requires both automatic performance analysis techniques and efficient multiprocessors configuration performance evaluation. Pr...
Riad Ben Mouhoub, Omar Hammami
TCAD
2008
93views more  TCAD 2008»
13 years 7 months ago
Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion
Starting at the 65-nm node, stress engineering to improve the performance of transistors has been a major industry focus. An intrinsic stress source--shallow trench isolation (STI)...
Andrew B. Kahng, Puneet Sharma, Rasit Onur Topalog...
SC
2009
ACM
14 years 2 months ago
FACT: fast communication trace collection for parallel applications through program slicing
A proper understanding of communication patterns of parallel applications is important to optimize application performance and design better communication subsystems. Communicatio...
Jidong Zhai, Tianwei Sheng, Jiangzhou He, Wenguang...