Sciweavers

360 search results - page 28 / 72
» Parallel processing flow models on desktop hardware
Sort
View
VLDB
2007
ACM
145views Database» more  VLDB 2007»
14 years 8 months ago
Executing Stream Joins on the Cell Processor
Low-latency and high-throughput processing are key requirements of data stream management systems (DSMSs). Hence, multi-core processors that provide high aggregate processing capa...
Bugra Gedik, Philip S. Yu, Rajesh Bordawekar
ISORC
2005
IEEE
14 years 2 months ago
Automated Model Checking and Testing for Composite Web Services
Web Services form a new distributed computing paradigm. Collaborative verification and validation are important when Web Services from different vendors are integrated together to...
Hai Huang, Wei-Tek Tsai, Raymond A. Paul, Yinong C...
SC
2009
ACM
14 years 3 months ago
Highly scalable genome assembly on campus grids
Bioinformatics researchers need efficient means to process large collections of sequence data. One application of interest, genome assembly, has great potential for parallelizati...
Christopher Moretti, Michael Olson, Scott J. Emric...
DATE
2002
IEEE
102views Hardware» more  DATE 2002»
14 years 1 months ago
Improving Placement under the Constant Delay Model
In this paper, we show that under the constant delay model the placement problem is equivalent to minimizing a weighted sum of wire lengths. The weights can be efficiently compute...
Kolja Sulimma, Wolfgang Kunz, Ingmar Neumann, Luka...
FPL
2007
Springer
94views Hardware» more  FPL 2007»
14 years 2 months ago
A Many-core Implementation based on the Reconfigurable Mesh Model
The reconfigurable mesh is a model for massively parallel computing for which many algorithms with very low complexity have been developed. These algorithms execute cycles of bus...
Heiner Giefers, Marco Platzner