770 search results - page 38 / 154 » Parallel simulation of chip-multiprocessor architectures |
CCGRID
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper focuses on architecture suitable for largescale simulation system. Based on the scenario of large-scale internet simulation, the grid technology is introduced and a new...
AINA
2007
IEEE
14 years 2 months ago
2007
IEEE
Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processor cores on the same chip. Chip-multiprocessor...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
CODES
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper presents a software implementation of a very fast parallel Reed-Solomon decoder on the second generation of MorphoSys reconfigurable computation platform, which is targ...
ISCA
2000
IEEE
14 years 27 days ago
2000
IEEE
Speculative parallelization aggressively executes in parallel codes that cannot be fully parallelized by the compiler. Past proposals of hardware schemes have mostly focused on si...