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ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
14 years 24 days ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
CGO
2004
IEEE
13 years 11 months ago
Custom Data Layout for Memory Parallelism
In this paper, we describe a generalized approach to deriving a custom data layout in multiple memory banks for array-based computations, to facilitate high-bandwidth parallel mem...
Byoungro So, Mary W. Hall, Heidi E. Ziegler
ISCC
2005
IEEE
119views Communications» more  ISCC 2005»
14 years 1 months ago
A Systematic Approach to Building High Performance Software-Based CRC Generators
—A framework for designing a family of novel fast CRC generation algorithms is presented. Our algorithms can ideally read arbitrarily large amounts of data at a time, while optim...
Michael E. Kounavis, Frank L. Berry
ARCS
2004
Springer
14 years 1 months ago
Reconfigurable OPTO-ASICs as base for future self-organizing CMOS cameras
: We investigated different parallel SIMD (single instruction multiple data) architectures based on pure programmable and reconfigurable approaches for their appropriateness for in...
Dietmar Fey, Daniel Schmidt 0003, Andreas Loos
VISUALIZATION
2005
IEEE
14 years 1 months ago
A Shader-Based Parallel Rendering Framework
Existing parallel or remote rendering solutions rely on communicating pixels, OpenGL commands, scene-graph changes or application-specific data. We propose an intermediate soluti...
Jérémie Allard, Bruno Raffin