Sciweavers

134 search results - page 10 / 27
» Parallelism through Digital Circuit Design
Sort
View
CDES
2006
99views Hardware» more  CDES 2006»
13 years 9 months ago
Realization of Digital Fuzzy Operations Using Multi-Valued Fredkin Gates
Multi-valued Fredkin gates (MVFG) are reversible gates and they can be considered as modified version of the better known reversible gate the Fredkin gate. Reversible logic gates ...
Amin Ahsan Ali, Hafiz Md. Hasan Babu, Ahsan Raja C...
ISCAS
2005
IEEE
132views Hardware» more  ISCAS 2005»
14 years 1 months ago
A high performance distributed-parallel-processor architecture for 3D IIR digital filters
—Real-time spatio-temporal VLSI 3D IIR digital filters may be used for imaging or beamforming applications employing 3D input signals from synchronously-sampled multi-sensor arra...
Arjuna Madanayake, Leonard T. Bruton
DATE
2003
IEEE
102views Hardware» more  DATE 2003»
14 years 27 days ago
Power Constrained High-Level Synthesis of Battery Powered Digital Systems
We present a high-level synthesis algorithm solving the combined scheduling, allocation and binding problem minimizing area under both latency and maximum power per clock-cycle co...
S. F. Nielsen, Jan Madsen
ICCAD
2003
IEEE
105views Hardware» more  ICCAD 2003»
14 years 4 months ago
TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers
We present a new approach for TAM optimization and test scheduling in the modular testing of mixed-signal SOCs. A test planning approach for digital SOCs is extended to handle ana...
Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty
GLVLSI
1998
IEEE
124views VLSI» more  GLVLSI 1998»
13 years 12 months ago
Non-Refreshing Analog Neural Storage Tailored for On-Chip Learning
In this research, we devised a new simple technique for statically holding analog weights, which does not require periodic refreshing. It further contains a mechanism to locally u...
Bassem A. Alhalabi, Qutaibah M. Malluhi, Rafic A. ...