7092 search results - page 1375 / 1419 » Parallelizing constraint programs |
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
In this paper, we propose a novel on-chip voltage drop reduction technique for on-chip power delivery networks of VLSI systems in the presence of variational leakage current sourc...
ICCD
2002
IEEE
14 years 4 months ago
2002
IEEE
The requirements to system and software development tools brought up by the automotive industry differ from the requirements that other customers have. The important catchwords he...
ICCAD
2008
IEEE
14 years 4 months ago
2008
IEEE
Abstract— As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasing...
DAC
2009
ACM
14 years 2 months ago
2009
ACM
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
ICALP
2009
Springer
14 years 2 months ago
2009
Springer
Speed scaling is a power management technique that involves dynamically changing the speed of a processor. This gives rise to dualobjective scheduling problems, where the operating...