Parameter variation in scaled technologies beyond 90nm will pose a major challenge for design of future high performance microprocessors. In this paper, we discuss process, voltag...
Abstract— Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield...
— As CMOS technology enters the nanometer regime, the increasing process variation is bringing manifest impact on circuit performance. In this paper, we propose a Principle Hessi...
Alexander V. Mitev, Michael Marefat, Dongsheng Ma,...
The statistical variations in electrical parameters, such as transistor gain factors and interconnect resistances, due to variations in the manufacturing process are studied using...
Suriyaprakash Natarajan, Melvin A. Breuer, Sandeep...
This paper studies the impact of variability on the noise robustness of logic gates using noise rejection curves (NRCs). NRCs allow noise pulses to be modeled using magnitude-dura...