71 search results - page 6 / 15 » Parameterized Function Evaluation for FPGAs |
CODES
2005
IEEE
14 years 3 months ago
2005
IEEE
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
TACS
1994
Springer
14 years 1 months ago
1994
Springer
Abstract. We have designed a programming logic based on an integration of functional programming languages with classical set theory. The logic merges a classical view of equality ...
FPL
2006
Springer
14 years 1 months ago
2006
Springer
This paper presents a novel tool flow combining rewriting logic with hardware synthesis. It enables the automated generation of synthesizable VHDL code from mathematical equations...
FPGA
2010
ACM
14 years 6 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
DAC
2009
ACM
13 years 7 months ago
2009
ACM
For hardware security applications, the availability of secret keys is a critical component for secure activation, IC authentication and for other important applications including...