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VLSID
2005
IEEE
131views VLSI» more  VLSID 2005»
14 years 7 months ago
Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Sh...
ISSRE
2003
IEEE
14 years 19 days ago
Augmenting Simulated Annealing to Build Interaction Test Suites
Component based software development is prone to unexpected interaction faults. The goal is to test as many potential interactions as is feasible within time and budget constraint...
Myra B. Cohen, Charles J. Colbourn, Alan C. H. Lin...
ATS
2003
IEEE
151views Hardware» more  ATS 2003»
14 years 20 days ago
BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability
A new technique for synthesizing totally symmetric Boolean functions is presented that achieves complete robust path delay fault testability. We apply BDDs for the synthesis of sy...
Junhao Shi, Görschwin Fey, Rolf Drechsler
ISQED
2007
IEEE
148views Hardware» more  ISQED 2007»
14 years 1 months ago
On Accelerating Soft-Error Detection by Targeted Pattern Generation
Soft error due to ionizing radiation is emerging as a major concern for future technologies. The measurement unit for failures due to soft errors is called Failure-In-Time (FIT) t...
Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu
GLVLSI
2002
IEEE
108views VLSI» more  GLVLSI 2002»
14 years 10 days ago
Protected IP-core test generation
Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte...
Alessandro Fin, Franco Fummi