149 search results - page 6 / 30 » Parametric Fault Simulation and Test Vector Generation |
ETS
2009
IEEE
13 years 5 months ago
2009
IEEE
We optimize the full-response diagnostic fault dictionary from a given test set. The smallest set of vectors is selected without loss of diagnostic resolution of the given test se...
ETS
2006
IEEE
14 years 1 months ago
2006
IEEE
A central problem in built-in self test (BIST) is how to efficiently generate a small set of test vectors that detect all targeted faults. We propose a novel solution that uses l...
ICCAD
1997
IEEE
13 years 11 months ago
1997
IEEE
We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed ...
GLVLSI
2002
IEEE
14 years 9 days ago
2002
IEEE
This paper develops new techniques for detecting both stuck-open faults and resistive open faults, which result in increased delays along some paths. The improved detection of CMO...
ICCAD
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper presents a novel concurrent fault simulator (called CONCERT) for nonlinear analog circuits. Three primary techniques in CONCERT, including fault ordering, state predict...