149 search results - page 9 / 30 » Parametric Fault Simulation and Test Vector Generation |
DATE
2000
IEEE
13 years 11 months ago
2000
IEEE
This paper describes an efficient error simulator able to analyze functional VHDL descriptions. The proposed simulation environment can be based on commercial VHDL simulators. Al...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Transparent-scan was proposed as an approach to test generation and test compaction for scan circuits. Its effectiveness was demonstrated earlier in reducing the test application ...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
This paper presents a novel approach for automatic test pattern generation of asynchronous circuits. The techniques used for this purpose assume that the circuit can only be exerc...
DDECS
2007
IEEE
13 years 9 months ago
2007
IEEE
— From an assumed property, which constrains the inputs of a design under test, we produce a RTL synthesizable design that generates compliant sequences of values for all the sig...
CDC
2009
IEEE
14 years 2 days ago
2009
IEEE
— The task in control allocation is to determine how to generate a specified generalized force from a redundant set of control effectors where the associated actuator control in...