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ICPADS
2006
IEEE
14 years 4 months ago
Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edw...
DAC
1996
ACM
14 years 2 months ago
A Boolean Approach to Performance-Directed Technology Mapping for LUT-Based FPGA Designs
Abstract -- This paper presents a novel, Boolean approach to LUTbased FPGA technology mapping targeting high performance. As the core of the approach, we have developed a powerful ...
Christian Legl, Bernd Wurth, Klaus Eckl
TIP
2011
164views more  TIP 2011»
13 years 5 months ago
Multiregion Image Segmentation by Parametric Kernel Graph Cuts
Abstract—The purpose of this study is to investigate multiregion graph cut image partitioning via kernel mapping of the image data. The image data is transformed implicitly by a ...
Mohamed Ben Salah, Amar Mitiche, Ismail Ben Ayed
ICCV
2007
IEEE
15 years 3 days ago
Learning Higher-order Transition Models in Medium-scale Camera Networks
We present a Bayesian framework for learning higherorder transition models in video surveillance networks. Such higher-order models describe object movement between cameras in the...
Ryan Farrell, David S. Doermann, Larry S. Davis
ICCAD
2003
IEEE
136views Hardware» more  ICCAD 2003»
14 years 7 months ago
Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications
— Memory-intensive applications present unique challenges to an ASIC designer in terms of the choice of memory organization, memory size requirements, bandwidth and access latenc...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...