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» Partitioning of VLSI Circuits and Systems
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ISCAS
2003
IEEE
153views Hardware» more  ISCAS 2003»
14 years 20 days ago
A VLSI model of range-tuned neurons in the bat echolocation system
The neural computations that support bat echolocation are of great interest to both neuroscientists and engineers, due to the complex and extremely time-constrained nature of the ...
Matthew Cheely, Timothy K. Horiuchi
VLSID
2002
IEEE
115views VLSI» more  VLSID 2002»
14 years 7 months ago
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits
We describe a built-in test pattern generation method for scan circuits. The method is based on partitioning and storage of test sets. Under this method, a precomputed test set is...
Irith Pomeranz, Sudhakar M. Reddy
DAC
1995
ACM
13 years 11 months ago
A Survey of Optimization Techniques Targeting Low Power VLSI Circuits
—We survey state-of-the-art optimization methods that target low power dissipation in VLSI circuits. Optimizations at the circuit, logic, architectural and system levels are cons...
Srinivas Devadas, Sharad Malik
GECCO
2004
Springer
123views Optimization» more  GECCO 2004»
14 years 23 days ago
A Hybrid Genetic Approach for Circuit Bipartitioning
We propose a hybrid genetic algorithm for partitioning a VLSI circuit graph into two disjoint graphs of minimum cut size. The algorithm includes a local optimization heuristic whic...
Jong-Pil Kim, Yong-Hyuk Kim, Byung Ro Moon
VTS
2008
IEEE
104views Hardware» more  VTS 2008»
14 years 1 months ago
Signature Rollback - A Technique for Testing Robust Circuits
Dealing with static and dynamic parameter variations has become a major challenge for design and test. To avoid unnecessary yield loss and to ensure reliable system operation a ro...
Uranmandakh Amgalan, Christian Hachmann, Sybille H...