338 search results - page 65 / 68 » Partitioning of VLSI Circuits and Systems |
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
A SoC design for applications of OMA DRM 2 Agent in mobile phones is presented in this paper, which has been verified by Altera Stratix EP1S80B956C6 FPGA development board. Several...
SAMOS
2004
Springer
14 years 22 days ago
2004
Springer
In this paper we present a new approach for generating high-speed optimized event-driven register transfer level (RTL) compiled simulators. The generation of the simulators is part...
CF
2005
ACM
13 years 9 months ago
2005
ACM
Power consumption within the memory hierarchy grows in importance as on-chip data caches occupy increasingly greater die area. Among dynamic power conservation schemes, horizontal...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
The advent of strong multi-level partitioners has made topdown min-cut placers a favored choice for modern placer implementations. We examine terminal propagation, an important st...
ASAP
2008
IEEE
14 years 1 months ago
2008
IEEE
As semiconductor processing technology continues to scale down, managing reliability becomes an increasingly difficult challenge in high-performance microprocessor design. Transie...