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MICRO
2005
IEEE
126views Hardware» more  MICRO 2005»
14 years 1 months ago
Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System
Scheduling algorithms used in compilers traditionally focus on goals such as reducing schedule length and register pressure or producing compact code. In the context of a hardware...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...
VISUALIZATION
2005
IEEE
14 years 1 months ago
Batched Multi Triangulation
The Multi Triangulation framework (MT) is a very general approach for managing adaptive resolution in triangle meshes. The key idea is arranging mesh fragments at different resolu...
Paolo Cignoni, Fabio Ganovelli, Enrico Gobbetti, F...
KCAP
2009
ACM
14 years 18 days ago
An entropy inspired measure for evaluating ontology modularization
Ontology modularization has received growing interest from the research community lately, since it supports tasks such as ontology design/reuse and knowledge selection and integra...
Paul Doran, Valentina A. M. Tamma, Terry R. Payne,...
IPPS
1999
IEEE
14 years 7 days ago
Hardwired-Clusters Partial-Crossbar: A Hierarchical Routing Architecture for Multi-FPGA Systems
Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing archit...
Mohammed A. S. Khalid, Jonathan Rose
FCCM
1997
IEEE
199views VLSI» more  FCCM 1997»
14 years 5 days ago
The RAW benchmark suite: computation structures for general purpose computing
The RAW benchmark suite consists of twelve programs designed to facilitate comparing, validating, and improving reconfigurable computing systems. These benchmarks run the gamut o...
Jonathan Babb, Matthew Frank, Victor Lee, Elliot W...