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MICRO
2008
IEEE
84views Hardware» more  MICRO 2008»
14 years 3 months ago
A performance-correctness explicitly-decoupled architecture
Optimizing the common case has been an adage in decades of processor design practices. However, as the system complexity and optimization techniques’ sophistication have increas...
Alok Garg, Michael C. Huang
RTCSA
2007
IEEE
14 years 2 months ago
An MPSoC Performance Estimation Framework Using Transaction Level Modeling
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
Rabie Ben Atitallah, Smaïl Niar, Samy Meftali...
ISCA
2011
IEEE
270views Hardware» more  ISCA 2011»
13 years 8 days ago
Sampling + DMR: practical and low-overhead permanent fault detection
With technology scaling, manufacture-time and in-field permanent faults are becoming a fundamental problem. Multi-core architectures with spares can tolerate them by detecting an...
Shuou Nomura, Matthew D. Sinclair, Chen-Han Ho, Ve...
HPCA
2008
IEEE
14 years 9 months ago
PaCo: Probability-based path confidence prediction
A path confidence estimate indicates the likelihood that the processor is currently fetching correct path instructions. Accurate path confidence prediction is critical for applica...
Kshitiz Malik, Mayank Agarwal, Vikram Dhar, Matthe...
ICCAD
2003
IEEE
190views Hardware» more  ICCAD 2003»
14 years 5 months ago
IDAP: A Tool for High Level Power Estimation of Custom Array Structures
—While array structures are a significant source of power dissipation, there is a lack of accurate high-level power estimators that account for varying array circuit implementat...
Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt,...